www.azmicrotek.com 1630 s stapley dr, suite 127 +1 - 480- 962- 5881 mesa, az 85204 usa request a sample may 2012, rev 1.0 d escription the azp92 is a 1 or 2 clock generation part specifically designed to accommodate colpitts or pierce based oscillators. features are incorporated to reduce board components. a voltage reference and input biasing allows for easy oscillator interface. the azp92 prov ides a 2 mode of operation for more frequency options and is selectable with a single connection. a selectable enable is also provided which doubles as a reset when the azp92 is in 2 mode. with a single connection, the enable can be selected to operate as active high or active low. b lock d iagram f eatures ? 3.0v to 5.5v operation ? selectable divide ratio ? selectable enable polarity and threshold (cmos or pecl) ? high bandwidth o 1.5+ ghz (1) o 3.0 + ghz (2) ? - 145 dbc/hz (1) typical noise floor ? - 151 dbc/hz (2) typical noise floor a pplications ? colpitts or pierce based oscillators p ackage a vailability ? mlp 8 o green/rohs compliant/pb - free az p92 pecl/ecl 1, 2 clock generation chip with selectable enable part number ( pn) package marking azp92nag 1 mlp8 p1g 2 1 ta pe & reel - add 'r1' at end of pn for 7in (1k parts), 'r2' (2.5k) for 13in 2 see www.azmicrotek.com for date code format www.azmicrotek.com
arizona microtek, inc. az p92 pecl/ecl 1, 2 clock generation chip with selectable enable www.azmicrotek.com +1 - 480- 962- 5881 2 request a sample may 2012, rev 1.0 p in d escription and c onfiguration table 1 - pin description pin name type function 1 en - sel input enable polarity select 2 d input data input 3 v bb input reference voltage 4 en input output enable 5 div - sel input divide select 6 q output inverted pecl output 7 q output pecl output 8 v cc power positive supply 9 v ee power negative supply d 4 3 2 1 6 5 8 7 en q v cc v ee en-sel q div-sel v bb figure 1 - pin configuration
arizona microtek, inc. az p92 pecl/ecl 1, 2 clock generation chip with selectable enable www.azmicrotek.com +1 - 480- 962- 5881 3 request a sample may 2012, rev 1.0 e ng ineering n otes the azp9 2 ?s divide ratio is selected with the div - s el pin. when div - sel is open (nc ), the azp9 2 functions as a standard receiver. when the div - sel is connected to v ee , it functions as a 2 divider. in 2 mode, the latches reset to a logic 0 level when disabled. the enable (en) functionality is selected w ith the en - sel pin which has three valid stat es: open (nc), v ee , or connected to v ee via a 20k ? resistor. leaving en - sel open or connecting it to v ee will select the en pin to function as an active high cmos/ttl enable. when en - sel is open, an internal 75 k ? pull - up resistor is selected which enables the outputs whenever en is left open. when en - sel is connected to v ee , an internal 75k ? pull - down resistor is selected which disables the ou tputs whenever en is left open. connecting the en - sel to v ee with a 20k ? r esistor will select the en pin to function as an active low pecl/ecl enable with an internal 75k ? pull - down resistor. in this mode, outputs are enabled when en is left open . this default logic condition can be overridden by connecting the en to v cc with an external resistor of 20k ? . table 2 - divide truth table div - sel ratio nc 1 v ee 1 2 1 div - sel connection must be 1 ? . table 3 - enable truth table en - sel en q q nc cmos low or v ee low high cmos high, v cc or nc data data v ee cmos low, v ee or nc low high cmos high or v cc data data 20k ? to v ee pecl low, v ee or nc low high pecl high or v cc data data figure 2 illustrates the timing sequences for the azp92 in the 1 mode which is determined by leaving the div - sel open (nc). it also illustrates the enable in the active high mode being controlled by a cmos signal. this mode is determined by leaving the en - sel open (nc). q d en (cmos) figure 2 - timing diagram
arizona microtek, inc. az p92 pecl/ecl 1, 2 clock generation chip with selectable enable www.azmicrotek.com +1 - 480- 962- 5881 4 request a sample may 2012, rev 1.0 figure 3 illustrates th e timing sequences for the azp92 in the 2 mode which is determined by connecting the div - sel to v ee . it also illustrates the enable in the active low mode being controlled by a pecl signal. this mode is determined by connecting the en - sel to v ee via 20k ? resistor. q d en (pecl) figure 3 - timing diagram figure 4 - typical large signal output swing measured with 750mv d input, q/ q each terminated to v cc - 2v via 50 resistors 200 300 400 500 600 700 800 900 1000 0 1000 2000 3000 4000 5000 6000 v outpp (mv) input frequency (mhz)
arizona microtek, inc. az p92 pecl/ecl 1, 2 clock generation chip with selectable enable www.azmicrotek.com +1 - 480- 962- 5881 5 request a sample may 2012, rev 1.0 p erformance data table 4 - absolute maximum ratings absolute maximum ratings are those values beyond which device life may be impaired. symbol characteristic c ondition rating unit v cc power supply v ee = 0v 0 to + 6.0 v v i input voltage v ee = 0v 0 to + 6.0 v v d/ d d/ d input voltage referenced to v bb 1.2 v i out output current continuous 50 ma surge 100 t a operating temperature range - - 40 to +85 c t stg storage temperature range - - 65 to +150 c esd hbm human body model electro static discharge - 2500 v esd m m machine model electro static discharge - 200 v esd cd m charged device model electro static discharge - 2000 v table 5 - 100k ecl dc characteristics 100k ecl dc characteristics (v ee = - 3.0v to - 5.5v, v cc = gnd) symbol characteristic - 40 c 0 c 25 c 85 c unit min max min max min max min max v oh output high voltage 1 - 1085 - 880 - 1025 - 880 - 1025 - 880 - 1025 - 880 mv v ol output low voltage 1 - 1900 - 1555 - 1900 - 1620 - 1900 - 1620 - 1900 - 1620 mv v bb reference voltage - 1390 - 1250 - 1390 - 1250 - 1390 - 1250 - 1390 - 1250 mv v ih input high voltage d /en 2 - 1165 - 390 - 1165 - 390 - 1165 - 390 - 1165 - 390 mv input high voltage en 3 v ee + 2000 v cc v ee + 2000 v cc v ee + 2000 v cc v ee + 2000 v cc mv v il input low voltage d/en 2 - 2250 - 1475 - 2250 - 1475 - 2250 - 1475 - 2250 - 1475 mv input low voltage en 3 v ee v ee + 800 v ee v ee + 800 v ee v ee + 800 v ee v ee + 800 mv i ih input high current en 150 150 150 150 a i il input low current en (ecl) 0.5 0.5 0.5 0.5 a i ee power supply current 4 31 31 31 34 ma 1. specified with outputs terminated through 50 ? resistors to v cc - 2v. 2. en - sel connected to v ee through a 20k ? resistor. 3. en - sel connected v ee or left open (nc). 4. div - sel left open (nc).
arizona microtek, inc. az p92 pecl/ecl 1, 2 clock generation chip with selectable enable www.azmicrotek.com +1 - 480- 962- 5881 6 request a sample may 2012, rev 1.0 table 6 - 100k lvpecl dc characteristics 100k lvpecl dc characteristics (v ee = gnd, v cc = +3.3v) symbol characteristic - 40 c 0 c 25 c 85 c unit min max min max min max min max v oh output high voltage 1,2 - 1085 - 880 - 1025 - 880 - 1025 - 880 - 1025 - 880 mv v ol output low voltage 1,2 - 1900 - 1555 - 1900 - 1620 - 1900 - 1620 - 1900 - 1620 mv v bb reference voltage 1 - 1390 - 1250 - 1390 - 1250 - 1390 - 1250 - 1390 - 1250 mv v ih input high voltage d 1,3 - 1165 - 390 - 1165 - 390 - 1165 - 390 - 1165 - 390 mv input high voltage en 1,4 - 1165 v cc - 1165 v cc - 1165 v cc - 1165 v cc mv v il input low voltage 1,3 - 2250 - 1475 - 2250 - 1475 - 2250 - 1475 - 2250 - 1475 mv input low voltage en 1,4 v ee - 1475 v ee - 1475 v ee - 1475 v ee - 1475 mv i ih input high current en 150 150 150 150 a i il input low current en (ecl) 0.5 0.5 0.5 0.5 a i ee power supply current 2 31 31 31 34 ma 1. for supply voltages other that 3.3v, use the ecl table values and add supply voltage value. 2. specified with outputs terminated through 50 ? resistors to v cc - 2v. 3. en - sel connected to v ee through a 20k ? resistor. 4. en - sel connected v ee or left open (nc). 5. div - sel left open (nc). table 7 - 100k pecl dc characteristics 100k pecl dc characteristics (v ee = gnd, v cc = +5.0v) symbol characteristic - 40 c 0 c 25 c 85 c unit min max min max min max min max v oh output high voltage 1,2 - 1085 - 880 - 1025 - 880 - 1025 - 880 - 1025 - 880 mv v ol output low voltage 1,2 - 1900 - 1555 - 1900 - 1620 - 1900 - 1620 - 1900 - 1620 mv v bb reference voltage 1 - 1390 - 1250 - 1390 - 1250 - 1390 - 1250 - 1390 - 1250 mv v ih input high voltage d 1,3 - 1165 - 390 - 1165 - 390 - 1165 - 390 - 1165 - 390 mv input high voltage en 1,4 - 1165 v cc - 1165 v cc - 1165 v cc - 1165 v cc mv v il input low voltage 1,3 - 2250 - 1475 - 2250 - 1475 - 2250 - 1475 - 2250 - 1475 mv input low voltage en 1,4 v ee - 1475 v ee - 1475 v ee - 1475 v ee - 1475 mv i ih input high current en 150 150 150 150 a i il input low current en (ecl) 0.5 0.5 0.5 0.5 a i ee power supply current 2 31 31 31 34 ma 1. for supply voltages other that 5.0v, use the ecl table values and add supply voltage value. 2. specified with outputs terminated through 50 ? resistors to v cc - 2v. 3. en - sel connected to v ee through a 20k ? resistor. 4. en - sel connected v ee or left open (nc). 5. div - sel left open (nc).
arizona microtek, inc. az p92 pecl/ecl 1, 2 clock generation chip with selectable enable www.azmicrotek.com +1 - 480- 962- 5881 7 request a sample may 2012, rev 1.0 table 8 - ac characteristics ac characteristics (v ee = - 3.0v to - 5.5v; v cc =gnd or v ee =gnd; v cc = +3.0v to +5.5v) symbol characteristic - 40 c 0 c 25 c 85 c unit min typ max min typ max min typ max min typ max t plh /t phl propagation delay d to q 1 450 450 450 450 ps en to q 1 600 600 600 600 ps t skew duty cycle skew 2 5 20 5 20 5 20 5 20 ps v pp (ac) input swing 3 differential 150 1000 150 1000 150 1000 150 1000 mv single ended 4 300 2000 300 2000 300 2000 300 2000 mv t r /t f output rise/fall 1 (20% - 80%) 80 200 80 200 80 200 80 200 ps 1. specified with outputs terminated through 50 ? resistors to v cc - 2v. 2. duty cycle skew is the difference between a t plh and t phl propagation delay through a device. 3. the peak - to - peak input swing is the range for which ac parameters are guaranteed. 4. range valid for ac coupled signals only.
arizona microtek, inc. az p92 pecl/ecl 1, 2 clock generation chip with selectable enable www.azmicrotek.com +1 - 480- 962- 5881 8 request a sample may 2012, rev 1.0 p ackage d iagram mlp 8 green/rohs compliant/pb - free msl=1 arizona microtek, inc. reserves the right to change circuitry and specifications at any time without prior notice. arizona microtek, inc. makes no warr anty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does arizona microtek, inc. assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. arizona microtek, inc. does not convey any license rights nor the rights of others. arizona microtek, inc. products are not designed, intended or authorized for use as components in systems intended to support or sustain life, or for any other application in which the failure of the arizona microtek, inc. product could create a situation where personal injury or death may occur. should buyer purchase or use arizona microtek, inc. products for any such unintended or unauthorized application, buyer shall indemnify and hold arizona microtek, inc. and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expe nses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that arizona microtek, inc. was negligent regarding the design or manufacture of the part.
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